Hytec Electronics Ltd. |
IP-ADC-8401-L 8-CHANNEL ADC INDUSTRY PACK
Product Description
The Hytec IP-ADC-8401-L is a single-width Industry Pack that provides 8 channels of simultaneously sampled analogue to digital conversion with the following characteristics:-
Specifications
Size | Single width Industry Pack 1.8ins x 3.9 ins |
Operating temp | 0 to 45 deg C ambient |
Number of channels | 8 |
ADC resolution | 16 bits |
Diff. Non-linearity | Monotonic to 15 bits (at 50kHz throughput) |
Int. Non-linearity | +/-0.012% of full scale (at 50kHz throughput) |
Offset error | +/-6LSBs at 25 deg C |
Offset drift | +/-10uV per deg C typical |
Gain error | +/-0.05% |
Gain drift | 10 ppm per deg C typical |
Range | +/-5V full-scale |
Overvoltage | Protected to +/-40V differential |
Bandwidth | 1MHz |
Throughput | 100KHz max external clock |
Conversion time | 6.4us |
Acquisition time | 2us |
Slew rate | Equivalent to 4V per us |
Settling time | 18us to 0.01% of full scale |
SNR | 80dB at 10kHz typical |
SINAD | 80dB at 10kHz typical |
Isolation | 100V via opto-isolators (if externally powered) |
Data format | 16 bits straight binary |
Memory | 1M x 16 bits (128K conversions per channel) |
Power |
+5V @ 300mA typical +/-12V @ 200mA typical when switched to internal |
Operating Modes
There are three operating modes:-
Memory Map
There are two main conversion memories of 512k samples each (lower and upper
buffers). These are each divided
into eight segments allocated to conversions from ADC1 to ADC8. When the lower
buffer has been filled the Half
Full Flag status is set and when the upper memory is full the Full Flag status
is set.
Lower Conversion Memory | Upper Conversion Memory |
ADC8 conversions | ADC8 conversions |
ADC7 conversions | ADC7 conversions |
ADC6 conversions | ADC6 conversions |
ADC5 conversions | ADC5 conversions |
ADC4 conversions | ADC4 conversions |
ADC3 conversions | ADC3 conversions |
ADC2 conversions | ADC2 conversions |
ADC1 conversion 64k ADC1 conversion 64k-1 ADC1 conversion 2 |
ADC1 conversion 128k ADC1 conversion 128k-1 ADC1 conversion 64k+2 |
Memory Size
A bit in the control register of the 8401-L allows selection of either 1Mb memory (64K samples/channel) when set at logic 1 or 2Mb (128K samples/channel) when set at logic 0.
ADC Register Read Out
There are eight ADC buffer registers
(addresses 10hex – 1Ehex) which store the last sampled conversions
and may be read at any time. The channel order is channel 1 at address 10hex to
channel 8 at address 1E.
Data format is straight binary with 0000h representing –10v, 8000h 0V and
FFFFh, +10V.
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
Data | Data | Data | Data | Data | Data | Data | Data | Data | Data | Data | Data | Data | Data | Data | Data |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Application Registers
There are five application specific (I/O) registers; the CSR, the number of
samples per trigger, the conversion
pointer and the interrupt vector value.
Control and Status Register (CSR)
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
A | EX | ST | XC | ET | EE | FE | HE | IM | x | EII | MII | MIS | CC | F | HF |
A | Arm the ADCs. Allow conversions either continuous or triggered. Clears memory address counter when zero. |
EX | Enable trigger. If not set continuously sample at the clock rate. If set allows external trigger or software trigger |
ST | Software trigger. Triggers a programmed number of samples. ST is cleared on completion. |
XC | Enable the external clock. If 0 the internal
clock is used for the sample rate. If set true the external clock is used for the sample clock without frequency division. |
ET | If set masks on external enable signal to allow/inhibit triggering / sampling. (External enable=Strobe) |
EE | Enables interrupt at end of sampling sequence. |
FE | Enables interrupt when the upper conversion memory has been filled. (Memory Full). |
HE | Enables interrupt when the lower conversion memory has been filled. (Memory Half Full). |
CC | Conversions complete. Status bit set when the
number of programmed samples has been completed. Generates IRQ0* if set and EE is set to a logic 1. |
F | Full status. Set when the upper conversion memory has been filled. Generates IRQ0* if set and FE is set to a logic 1. |
HF | Half full status. Set when the lower conversion memory has been filled. Generates IRQ0* if set and HE is set to a logic 1. |
EII | Enable memory inhibit interrupts. |
MII | Signifies that an interrupt has been generated by memory inhibit being enabled. |
MIS | Inhibit memory set external signal asserted. |
IM | Enables 1Mbyte memory (64K samples/channel) when IM=1 and 2Mbyte (120K samples/channel) when IM=0. |
Conversion Pointer Base Address
The current conversion address is given by the conversion base address offset by the ADC number and the Half Full status. The conversion pointer base address is the number of conversions in the current memory.
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
C15 | C14 | C13 | C12 | C11 | C10 | C9 | C8 | C7 | C6 | C5 | C4 | C3 | C2 | C1 | C0 |
Number of conversions
The number of conversions register allows 64K of samples per trigger to be
programmed. If the memory buffer size is exceeded
the conversions will wrap around from the upper memory to the base of the lower
memory
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
N15 | N14 | N13 | N12 | N11 | N10 | N9 | N8 | N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0 |
Clock Rate
The clock rate register is a four bit register which enables codes 0 - 15 to
enable internal clock frequencies of 1 Hz to 100KHz
in multiples of 1,2,5 or 10. (E.g. 0=1Hz, 1=2Hz, 2=5Hz, 3=10Hz and so on)
Each clock pulse will initiate simultaneous ADC
conversions and store them in memory and to 8 ADC registers.
Interrupt Vector
The vector register is a 16 bit register which stores the interrupt vector value.
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
V15 | V14 | V13 | V12 | V11 | V10 | V9 | V8 | V7 | V6 | V5 | V4 | V3 | V2 | V1 | V0 |
ID PROM
The ID data conforms to ID PROM data Format II. The ID addresses are as below:-
Base +80 | ASCII 'VI' | 5649h | |
+82 | ASCII 'TA' | 5441h | |
+84 | ASCII '4' | 3420h | |
+86 | Hytec ID high byte | 0080h | |
+88 | Hytec ID low word | 0300h | |
+8A | Model number | 8401h | |
+8C | Revision | 5501h | PCB Issue 5 Firmware v5.01 |
+8E | Reserved | 0000h | |
+90 | Driver ID | 0000h | |
+92 | Driver ID | 0000h | |
+94 | Flags | 0002h | |
+96 | No of bytes used | 001Ah | |
+98 | Not used | 0000h | |
9A | Serial Numbers | xxxxdec |
The eight ADC buffer registers store the last sample conversions and may be
read at anytime. Data format is straight binary with
0000 representing -10V, 8000 (hex) = 0volts and FFFFh = +10V.
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | |
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | Data Bits |
HYTEC Head
Post : 5 Cradock Road, Reading, Berkshire, RG2 0JT, England. Phone : +44 (0)118 9757770 Fax : +44 (0)118 9757566 |
HYTEC