Hytec Electronics Ltd.

 

 

IP-DAC-8402 16-CHANNEL DAC INDUSTRY PACK

 

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Product Description

The Hytec IP-DAC-8402 is a single-width Industry Pack that provides 16 channels of simultaneously updated digital

to analogue conversion with the following characteristics:-

Specifications

Size Single width Industry Pack 1.8ins x 3.9 ins
Operating temp 0 to 45 deg C ambient
Number of channels: 16
DAC resolution: 16 bits
Data format: 16 bits binary
Range: +/-10V full-scale  (0 to10V model 8402-U) (+/-5V model 8402-L)
Output current: +/-10mA @ FS
Capacitive load: Stable up to 10000pF
Short circuit duration: Continuous
OverV withstand: No internal protection from external voltages provided
Update rate: 10KHz max
Power: +5V @ 300mA typical
+/-12V @ 200mA typical when switched to internal
Isolation: 100V via opto-isolators (if externally powered)
DAC device: Linear Technology LTC1655 with serial interface
Integral non-linearity: +/-8LSBs typ. +/-16LSBs max
Offset error: +/-2mV max (at zero volts and 25 deg C)
Offset drift: +/-5uV per deg C typical
Gain error: +/-5LSBs typ. +/-16LSBs max.
Output slew rate: +/-0.7V/us typ. +/-0.3V/us min.
Amplifier settling time: 20us max.to 0.005% of final value for 1000pF load capacitance

Operating Modes

There are two operating modes:-

1. Registered – the DAC outputs are controlled by the contents of the DAC registers.

2. Memory – the outputs are updated for the programmed number of samples at the programmed clock rate. All the outputs are updated serially but change together (there will be slight changes due to differences in the slew rate of the amplifiers (about +/-1uS) at the end of an internal update cycle. The outputs may be updated at a rate of up to 20KHz. The two methods to update the 8402 DACs are detailed below.

USING REGISTER TO UP DATE DACs
Using registers there are 16 registers one per channel. These can be loaded one at a time, the module can then be ARMed and the data from the registers will be serially loaded from one DAC to the next until all the data has been passed to the DACs. At this point the DAC outputs are automatically updated giving 16 simultaneous outputs. While the unit is ARMed the DACs are constantly refreshed with the contents of the registers which can be changed during this time. There is a delay which is fixed of approximately 32us after ARM is set, before all the outputs change together.

USING MEMORY TO UP DATE DACs
In this method the memory is first loaded with the required data and the number of memory locations used is entered in to the Number of Updates (NCO) register. The Control and Status Register (CSR) is then set to enable memory updates and ARM to unit with a software command. A trigger can then be issued either by a software command or by an external trigger to start down loading the data held in memory to the DACs via the registers as detail above. In this mode the registers are updated with new data from the memory at the update clock rate which is derived either internally or externally. The memory address is automatically incremented. When the programmed number of output has occurred the unit will stop and generate an interrupt if enabled or if set in continues mode the address counter will be zeroed and the output repeated (no interrupt generated in continues mode) until the ARM bit is cleared or the continues bit in the CSR is cleared.

Download User Manual

Ordering Information

Cat No Name Description
8402.1 IP-DAC-8402 16-channel 16bit DAC (+/-10V) O/P with function generator memory
8402.2 IP-DAC-8402-L 16-channel 16bit DAC (+/-5V) O/P with function generator memory
8402.3 IP-DAC-8402-U 16-channel 16bit DAC (+10V) O/P with function generator memory
Hytec Electronics Ltd
5 Cradock Road, Reading, Berkshire, RG2 0JT, England.
Phone : +44 (0)118 9757770
Fax : +44 (0)118 9757566



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